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Ordering number : EN6142
CMOS IC
LC75742E, 75742W
1/2 Duty VFD Driver with Key Input Function
Overview
The LC75742E and LC75742W are 1/2 duty VFD drivers that can be used for electronic tuning frequency display and other applications under the control of a microcontroller. These products can directly drive VFDs with up to 82 segments. It also includes a key scan circuit and can support input from up to 30 keys and can thus reduce the number of lines to the front panel in application systems.
Package Dimensions
unit: mm 3151-QFP64E
[LC75742E]
17.2 14.0 0.35
33 48 49 32
1.0 1.6 1.0
0.8
1.6 1.0
0.15
* Key input from up to 30 keys (Key scans are only performed when keys are pressed.) * 82 segment outputs. * Noise reduction circuits are built into the output drivers. * Serial data I/O supports CCB format communication with the system controller. * Dimmer and sleep mode can be controlled by serial data input. * High generality since display data is displayed without the intervention of a decoder. * All segments can be turned off with the BLK pin.
0.8
Features
17.2 14.0
17
1.0
64 1 16
3.0max 0.8
32 17
0.1 2.7
15.6
SANYO: QFP64E (QIP64E)
unit: mm 3190-SQFP64
[LC75742W]
12.0 10.0 1.25
48 49
0.5
0.18
1.25
33
0.15
12.0 10.0 0.5
64
1.25
1
16
0.5
0.1 0.5
1.7max
1.25
SANYO: SQFP64
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
43099TH (OT) No. 6142-1/18
LC75742E, LC75742W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum Supply voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 Output voltage VOUT2 VOUT3 IOUT1 Output current IOUT2 IOUT3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD VFL DI, CL, CE, BLK OSCI, KI1 to KI5 S1 to S41, G1, G2 OSCO, KS1 to KS6 DO S1 to S41 G1, G2 KS1 to KS6 Ta = 85C (LC75742E) Ta = 85C (LC75742W) Conditions Ratings -0.3 to +6.5 -0.3 to +21.0 -0.3 to +6.5 -0.3 to VDD +0.3 -0.3 to VFL +0.3 -0.3 to VDD +0.3 -0.3 to +6.5 6 60 1 400 300 -40 to +85 -50 to +150 Unit V V V V V V V mA mA mA mW mW C C
Input voltage
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Symbol VDD VFL VIH1 High-level input voltage VIH2 VIH3 Low-level input voltage Guaranteed oscillator frequency range Recommended external resistor value Recommended external capacitor value Clock low-level pulse width Clock high-level pulse width Data setup time Data hold time CE wait time CE setup time CE hold time DO output delay time DO rise time BLK switching time VIL fOSC ROSC COSC toL toH tds tdh tcp tcs tch tdc tdr tc VDD VFL DI, CL, CE, BLK OSCI KI1 to KI5 DI, CL, CE, BLK, OSCI, KI1 to KI5 OSCI, OSCO OSCI, OSCO OSCI, OSCO CL : See figure 1. CL : See figure 1. DI, CL : See figure 1. DI, CL : See figure 1. CE, CL : See figure 1. CE, CL : See figure 1. CE, CL : See figure 1. DO: RPU = 4.7 k, CL = 10 pF*: See figure 1. DO: RPU = 4.7 k, CL = 10 pF*: See figure 1. BLK, CE : See figure 4. 10 Conditions Ratings min 4.5 8 0.8 VDD 0.8 VDD 0.6 VDD 0 0.4 4.7 22 160 160 160 160 160 160 160 1.5 1.5 1.6 20 47 typ 5.0 12 max 5.5 18 5.5 VDD VDD 0.2 VDD 3.0 100 100 Unit V V V V V V MHz k pF ns ns ns ns ns ns ns s s s
Supply voltage
Note: Since DO is an open-drain output, these values will vary with the pull-up resistance RPU and the load capacitance CL.
No. 6142-2/18
LC75742E, LC75742W Electrical Characteristics in the Allowable Operating Ranges
Parameter Symbol IIH1 IIH2 IIL VIF RPD IOFFH VOH1 High-level output voltage VOH2 VOH3 VOH4 VOL1 Low-level output voltage VOL2 VOL3 VOL4 Oscillator frequency Hysteresis voltage Current drain fOSC VH IDD1 IDD2 Conditions DI, CL, CE, BLK: VIN = 5.5 V OSCI: VIN = VDD DI, CL, CE, BLK, OSCI: VIN = 0 V KI1 to KI5 KI1 to KI5: VDD = 5.0 V DO: VO = 5.5 V S1 to S41: IO = -2 mA G1, G2: IO = -50 mA OSCO: IO = -0.5 mA KS1 to KS6: IO = -500 A S1 to S41, G1, G2: IO = 50 A OSCO: IO = 0.5 mA KS1 to KS6: IO = 25 A DO: IO = 1 mA ROSC = 20 k, COSC = 47 pF DI, CL, CE, BLK, KI1 to KI5 Sleep mode Outputs open: fOSC = 1.6 MHz 0.2 0.5 0.1 1.6 0.1 VDD 5 10 VFL - 0.6 VFL - 1.3 VDD - 2.0 VDD - 1.2 VDD - 0.5 VDD - 0.2 0.5 2.0 1.5 0.5 50 100 -5 0.05 VDD 250 5 Ratings min typ max 5 5 Unit A A A V k A V V V V V V V V MHz V A mA
High-level input current Low-level input current Input floating voltage Pull-down resistance Output off leakage current
* When stopped with CL at the low level
* When stopped with CL at the high level
Figure 1
No. 6142-3/18
LC75742E, LC75742W Pin Assignment
LC75742E LC75742W
Top view
No. 6142-4/18
LC75742E, LC75742W Block Diagram
Pin Descriptions
Pin No. 3 59 56 58 57 Pin VFL VDD VSS OSCI OSCO Function Driver block power supply. Applications must provide a voltage in the range 8.0 to 18.0 V. Logic block power supply. Applications must provide a voltage in the range 4.5 to 5.5 V. Power supply ground. This pin must be connected to the system ground. Oscillator circuit connections. An oscillator circuit is formed by connecting a resistor and a capacitor externally to these pins. Reset signal input used to initialize the IC internal state. During a reset, the display is turned off forcibly regardless of the internal display data. Also note that the internal key data is all reset to 0 and key scan operations are disabled. However, serial data input is possible in this state. Serial data interface. These pins must be connected to the system microcontroller. Note that since DO is an open-drain output, a pull-up resistor is required. CL: Synchronization clock CE: Chip enable DI: Transfer data DO: Output data I/O -- -- -- I O Handling when unused -- -- -- GND OPEN
60
BLK
I
GND
63 64 62 61 1, 2 44 to 4 45 to 50 51 to 55
CL DI CE DO G1, G2 S1 to S41 KS1 to KS6 KI1 to KI5
I
GND
O O O O I
OPEN OPEN OPEN OPEN GND
Digit outputs. The frame frequency fO is (fOSC/4096) Hz. Segment outputs that display the display data transferred over the serial interface. Key scan outputs. Normally, when a key matrix is formed, diodes are inserted in the key scan timing lines to prevent shorts. However, since this IC uses unbalanced CMOS outputs in the output transistor circuit, the IC will not be damaged if these outputs are shorted. Key scan inputs. Pull-down resistors are built into the IC internal pin circuits.
No. 6142-5/18
LC75742E, LC75742W Serial Data Input * When stopped with CL at the low level
Note: don't care DD: Direction data
* When stopped with CL at the high level
Note: don't care DD: Direction data
Figure 2
* CCB address: Applications must send the value 01110001B (8EH) as shown in figure 2. * D1 to D41: Segment display data for the G1 digit output pin Dn (n = 1 to 41) = 1: Segment on Dn (n = 1 to 41) = 0: Segment off * D42 to D82: Segment display data for the G2 digit output pin Dn (n = 42 to 82) = 1: Segment on Dn (n = 42 to 82) = 0: Segment off * S0, S1: Sleep control data * DM0 to DM9: Dimmer data
No. 6142-6/18
LC75742E, LC75742W Control Data * S0, S1: Sleep control data This control data controls switching between sleep mode and normal mode, and also sets the states of the KS1 to KS6 key scan output pins in key scan standby mode.
Control data S0 0 0 1 1 S1 0 1 0 1 Mode Normal Sleep Sleep Sleep Clock generator (oscillator circuit) Oscillator operating Stopped Stopped Stopped Segment outputs Digit output Operating L L L Output pin states during key scan standby KS1 H L L H KS2 H L L H KS3 H L L H KS4 H L L H KS5 H L H H KS6 H H H H
* DM0 to DM9: Dimmer data This data controls the duty of the G1, G2 digit output pins. This data forms a 10-bit binary value in which D0 is the LSB. The brightness of the display can be controlled by adjusting the duty of the G1, G2 digit output pins. The table lists the relationship between the dimmer data and the dimmer value.
DM9 0 0 0 DM8 0 0 0 DM7 0 0 0 DM6 0 0 0 DM5 0 0 0 to 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 DM4 0 0 0 DM3 0 0 0 DM2 0 0 0 DM1 0 0 1 DM0 0 1 0 Dimmer value (t4/t3) 0/1024 1/1024 2/1024 to 1020/1024 1021/1024 1022/1024 Illegal setting
t3 and t4: See figure 5.
Relationship between the Display Data (D1 to D82) and the Segment Output Pins
Segment output pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 G1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 G2 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 Segment output pin S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 G1 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 G2 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 Segment output pin S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 G1 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 G2 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82
As an example, the table below lists the operation of the S11 segment output pin.
Display data D11 0 0 1 1 D52 0 1 0 1 Segment output pin (S11) state The segments corresponding to the G1 and G2 digit output pins are off The segment corresponding to the G2 digit output pin is turned on The segment corresponding to the G1 digit output pin is on The segments corresponding to the G1 and G2 digit output pins are on
No. 6142-7/18
LC75742E, LC75742W Serial Data Output * When stopped with CL at the low level
* When stopped with CL at the high level
Figure 3
* CCB address: Applications must send the value 11110001B (8FH) as shown in figure 3. * KD1 to KD30: Key data * SA: Sleep acknowledge data
Note: The key data (KD1 to KD30) and the sleep acknowledge data (SA) will be invalid if the key data is read when DO is high.
No. 6142-8/18
LC75742E, LC75742W Output Data * KD1 to KD30: Key data These bits represent the key output states when a key matrix with up to 30 keys is formed using the KS1 to KS6 key scan output pins and the KI1 to KI5 key scan input pins. When a key is pressed, the bit corresponding to that key will be set to 1. The correspondence is listed in the following table.
Item KS1 KS2 KS3 KS4 KS5 KS6 KI1 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30
* SA: Sleep acknowledge data This output data is set to the state when the key was pressed. In that case DO will go to the low level. If serial data is input during this period and the mode is set (normal mode or sleep mode), the IC will be set to that mode. SA is set to 1 in the sleep mode and to 0 in the normal mode. Sleep Mode The IC is set to sleep mode by setting either S0 or S1 in the control data to 1. The segment outputs and the digit outputs are all set low, and the clock generator (oscillator circuit) is stopped (although it is restarted when a key is pressed), and thus power dissipation is reduced. This mode is cleared by setting S0 and S1 in the control data to 0.
Key Scan Operation * Key scan timing The scan period is 12000T [s]. A key scan is performed twice to reliably recognize the key on/off states by verifying that the key data for the two scans agrees. If the data agrees, the IC recognizes a key press and 25600T [s] after the start of key scan execution issues a key scan data read request by outputting a low level from DO. If the key data does not agree and a key was pressed at the later scan, the IC executes another key scan operation. Note that this means that this IC cannot recognize a key press shorter than 25600T [s].
Note *: The high-level and low-level states in sleep mode are set according to the control data S0 and S1. Key scan output signals are not output from pins set to the "L" state.
No. 6142-9/18
LC75742E, LC75742W * In normal mode -- The pins KS1 to KS6 are set high. -- A key scan is started when any of the keys is pressed, and the keys are kept scanning until all keys are released. The controller can recognize simultaneous multiple key presses by checking the key data for multiple bits being set. -- If a key is pressed for over 25600T [s] (where T = 1/fOSC), the IC outputs a key data read request to the controller by setting DO low. The controller acknowledges this state and reads the key data. However, note that DO will go high when CE is set high during the serial data transfer. -- After the controller key data readout completes, the key data read request will be cleared (DO will be set high), and the IC performs another key scan. Note that since DO is an open-drain output, a pull-up resistor (between 1 and 10 k) is required.
Key input 1
Key input 2
Key scan
Serial data transfer
Serial data transfer
Key address (8FH)
Serial data transfer
Key address
Key address
Key data read Key data read request
Key data read Key data read request
Key data read Key data read request
* In sleep mode -- The pins KS1 to KS6 are set to high or low according to the values of S0 and S1 in the control data. (See the description of the control data elsewhere in this document.) -- If a key connected to one of the KS1 to KS6 lines that was set high is pressed, the clock generator (oscillator circuit) is started and a key scan is performed, and the keys are kept scanning until all keys are released. The controller can recognize simultaneous multiple key presses by checking the key data for multiple bits being set. -- If a key is pressed for over 25600T [s] (where T = 1/fOSC), the IC outputs a key data read request to the controller by setting DO low. The controller acknowledges this state and reads the key data. However, note that DO will go high when CE is set high during the serial data transfer. -- After the controller key data readout completes, the key data read request will be cleared (DO will be set high), and the IC performs another key scan. However, sleep mode will not be cleared. Note that since DO is an open-drain output, a pull-up resistor (between 1 and 10 k) is required. -- Example of a key scan operation in sleep mode Example: Sleep mode with S0 = 0, S1 = 1 (Only KS6 is set high)
If one of these keys is pressed, clock generator (oscillator circuit) is started and a key scan is performed.
Note *: These diodes are required to reliably recognize multiple key presses on the KS6 line when the IC is set to sleep mode with only KS6 set to high as in the example above. That is, they prevent incorrect recognition of key presses due to sneak currents arising from simultaneous presses of keys on the KS1 through KS5 lines.
No. 6142-10/18
LC75742E, LC75742W
Key input (KS6 line)
Key scan
Serial data transfer
Serial data transfer
Key address (8FH)
Serial data transfer
Key address
Key data read Key data read request
Key data read Key data read request
Multiple Key Presses The LC75742E/W, even without diodes in the key scan lines, can scan for any combination of dual key presses, any combination of triple key presses on any of the KI1 to KI5 key scan input pin lines, or any combination of multiple key presses on any of the KS1 to KS6 key scan output lines. However, keys that are not pressed may be seen as having been pressed for any other multiple key press combination. Accordingly, applications must insert diodes at each key. Also, to reject any triple and higher multiple key presses, if three or more data readout are 1 ignore the data by the software or in other ways. Notes on the BLK Pin and Display Control Since the states of the IC internal data (D1 to D82, and the control data) are undefined when power is first applied, applications should turn off the display (i.e. set S1 to S41, and G1 and G2 low) by setting the BLK pin low at the same time as power is applied. Applications should transfer all 128 bits of the serial data while BLK is held low, and only then set BLK high. This will prevent random meaningless display at power on. (See figure 4.) Note on the Power on Sequence Applications must observe the following sequences when turning the power on or off. * At power on: First turn on the logic system power (VDD), and then turn on the driver power (VFL) * At power off: First turn off the driver power (VFL), and then turn off the logic system power (VDD).
Figure 4
No. 6142-11/18
LC75742E, LC75742W Output Waveforms (S1 to S41)
G1
G2
S1 to S41 waveform when the segment corresponding to G1 is on.
S1 to S41 waveform when the segment corresponding to G2 is on.
S1 to S41 waveform when the seguments corresponding to G1 and G2 are on.
S1 to S41 waveform when the seguments corresponding to G1 and G2 are off.
No. 6142-12/18
LC75742E, LC75742W Relationship between the Segment and Digit Outputs
S1 to S41
Example 1
Example 2
Example 3
Figure 5 * Figure 5 shows the case where the display data is set up so that the segment outputs S1 to S41 output the VSS level with the same timing as the G1 and G2 digit outputs, and output the VFL level with the same timing as the G2 digit output. Here, the segments corresponding to G2 will be turned on. The relationship between t3 and the oscillator frequency fOSC in this case is t3 = 2048/fOSC. * The G1 and G2 digit output waveforms in example 1 correspond to a dimmer data (DM0 to DM9) set to 3FEH. The relationship between t1 and the oscillator frequency fOSC is t1 = 2/fOSC. Note that t1 and t2 in example 1 are identical times. * The G1 and G2 digit output waveforms in example 2 correspond to a dimmer data (DM0 to DM9) set to a smaller value. Although t1 does not change, t2 becomes longer. Here, if the dimmer data (DM0 to DM9) is set to 1FFH and the oscillator frequency fOSC is 1.6 MHz, then t2 can be calculated as follows. t2 = t3 - t1 x (1FFH +1) = 1024 fOSC
= 0.64 [ms] * If the dimmer data (DM0 to DM9) is set to an even smaller value, t2 will become even longer as shown in example 3. Note that t1 does not change in this case as well.
No. 6142-13/18
LC75742E, LC75742W Block States during the Reset Period (when BLK is low) * Divider and timing generator These circuits are reset and their base clock is stopped. * Dimmer timing generator The circuit is reset and its operation is stopped. * Digit and segment drivers These circuits are reset and the display is turned off (S1 to S41 and G1 and G2 are set low.) * Key scan The circuit is reset, its internal circuits are set to the initial state, and key scanning is disabled. * Key buffer The circuit is reset and all data is set to 0. * Clock generator The state (normal or sleep mode) of this block (the clock oscillator circuit) is determined after the sleep control data (S0 and S1) is transferred. * CCB interface, shift register, control register, latch, and multiplexer These circuits are not reset so that serial data can be input during the reset period.
DIGIT DRIVER
SEGMENT DRIVER
DIMMER TIMING GENERATOR
TIMING GENERATOR DIVIDER
KEY BUFFER
KEY SCAN
: Blocks that are reset.
No. 6142-14/18
LC75742E, LC75742W Output Pin States during the Reset Period (when BLK is low)
Output pin S1 to S41 G1, G2 KS1 to KS5 KS6 DO State during reset L L X *1 H H *2
Notes: 1. The state of this pin is undefined after power has been applied until the sleep control data (S0 and S1) are transferred. 2. Since this pin is an open-drain output, a pull-up resistor (between 1 and 10 k) is required. It remains high during the reset period even if the controller attempts to read the key data.
Sample Application Circuit
From the controller To the controller To the controlle power supply
Key matrix with up to 30 keys
Note *: Since DO is an open-drain output, a pull-up resistor is required. Select a value in the range 1 to 10 k that is most appropriate for the capacitance of the external lines so that the waveform is not distorted.
Notes on the Segment and Digit Waveforms
Segment waveform
Digit waveform 1
Digit waveform 2
Figure 6 The segment waveform is somewhat deformed due to the VFD panel itself and the circuit wiring. Furthermore, if a digit waveform such as digit waveform 1 in which no dimming is applied is used, the display will glow dimly. Therefore, applications must take this waveform deformation into account and apply adequate dimming such as that shown in digit waveform 2 so that this phenomenon does not occur.
No. 6142-15/18
VFD panel with up to 82 segments
LC75742E, LC75742W Notes on Controller Transfer of Display Data Since the display data (D1 to D82) is transferred in two operations as shown in figure 2, we strongly recommend that applications transfer all the data within a 30 ms period to assure display quality. Controller Key Data Readout Procedure When the controller uses a timer to read out the key data * Flowchart
* Timing chart
Controller determination (Key on)
Controller determination (Key on)
Controller determination (Key off)
Controller determination (Key on)
Controller determination (Key off)
t5 .........Key scan execution time (25600T [s]) when the key data for two key scan operations matches. t6 ........Key scan execution time (51200T [s]) when the key data for the first two key scan operations 1 ............does not match. T= [s] fOSC t7 .........Key address (8FH) transfer time t8 .........Key data readout time * Operation When the controller use timer processing for key on/off determination and key data readout, it must set CE low and check the state of DO at least once every t9 period. If DO is low, the controller must recognize that a key has been pressed and read out the key data. The period t9 must obey the following inequality: t9 > t7 + t8 + t6 Note that if the controller reads out key data when DO is high, both the key data (KD1 to KD30) and the sleep acknowledge data will be invalid data.
No. 6142-16/18
LC75742E, LC75742W When the controller uses interrupt processing to read out the key data * Flowchart
Wait period (at least t10)
* Timing chart
Controller determination (Key on)
Controller Controller determination determination (Key off) (Key on)
Controller determination (Key on)
Controller determination (Key on)
Controller determination (Key off)
t5.........Key scan execution time (25600T [s]) when the key data for two key scan operations matches. t6 ........Key scan execution time (51200T [s]) when the key data for the first two key scan operations ............does not match. 1 t7......... Key address (8FH) transfer time T= [s] fOSC t8.........Key data readout time * Operation When the controller uses interrupt processing for key on/off determination and key data readout, it must check the state of DO when CE is low, and perform a key data readout if DO is low. The next time the controller checks the on/off states of the keys, it must make that determination at a time t10 after the last readout based on the state of DO when CE is low, and then read out the key data. The time t10 must obey the following inequality: t10 > t6 Note that if the controller reads out key data when DO is high, both the key data (KD1 to KD30) and the sleep acknowledge data will be invalid data.
No. 6142-17/18
LC75742E, LC75742W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of April, 1999. Specifications and information herein are subject to change without notice. PS No. 6142-18/18

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